1. Field of the Invention
The present invention relates to a device for testing a semiconductor device and more particularly to an improvement for generating a test signal with a small-scale structure.
2. Description of the Background Art
FIG. 3 is a block diagram showing a conventional device for testing a semiconductor device. In FIG. 3, numeral 1 designates a CPU for controlling each section in the test device 100. A command from the CPU 1 is transmitted through a CPU bus 2 to each section in the test device 100. The test device 100 is provided with a plurality of external signal terminals 3a, 3b, . . . 3n, which are connected to each pin of a semiconductor device 200 to be tested.
Pin test portions 4a, 4b, . . . 4n are provided correspondingly to the external signal terminals 3a, 3b, . . . 3n, respectively. Each of the pin test portions 4a, 4b, . . . 4n is composed of a pattern memory 5, a timing memory 6, a timing generator 7, an output waveform generation circuit 8 and a comparator 9. The pattern memory 5 stores data on logical patterns of a test signal for the corresponding pins of the semiconductor device 200 to be tested and data on logical patterns of judgement. The timing memory 6 stores data on timings in which the test signal is applied and data on timings of judgement. The timing generator 7 generates a timing signal TM on the basis of data which is read out from the timing memory 6. The output waveform generation circuit 8 generates an output waveform on the basis of pattern data PT which is read out from the pattern memory 5 and the timing signal TM and outputs it as a test signal TS to the corresponding external siganl terminal 3a, 3b, . . . 3n. The comparator 9 samples a response output from the semiconductor device 200 to be tested in the timing of the timing signal TM outputted from the timing generator 7 to make a judgement by comparing the sampled data with the pattern data PT outputted from the pattern memory 5.
The test device 100 is provided with a pattern controller 10, an instruction memory 11, a period memory 12 and a test synchronizing signal generator 13, which are common to each of the pin test portions 4a, 4b, . . . 4n. The pattern controller 10 controls the sequences of generating the test signal and executing the judgement in each of the pin test portions 4a, 4b, . . . 4n, and others. The instruction memory 11 stores programs which specify an operation process of the pattern controller 10. The period memory 12 stores period data which specify a period of a test synchronizing signal SY for synchronizing each of the pin test portions 4a, 4b, . . . 4n with each other. The test synchronizing signal generator 13 generates the test synchronizing signal SY in accordance with the period data being read out from the period memory 12.
Next, an operation of the device is explained, referring to FIG. 4. A test program produced by the CPU 1 is transmitted through the CPU bus 2 to the pattern memories 5, the timing memories 6, the instruction memory 11 and the period memory 12 to be stored therein. Normally, the contents of the pattern memories 5 have a value "0" or "1", those of the timing memories 6 have a value indicating an address of a timing edge data table 7a in the timing generator 7, and those of the period memory 12 have a value indicating an address of a test synchronizing signal timing data table 13a in the test synchronizing signal generator 13, as shown in FIG. 4.
When a test start command is supplied by the CPU 1 to the pattern controller 10, the pattern controller 10 transmits a start address to the pattern memories 5, the timing memories 6, the instruction memory 11 and the period memory 12. Subsequently, addresses determined in accordance with the contents of the instruction memory 11 are transmitted to the memories 5, 6, 11 and 12. The contents of the respective memories 5, 6, 11 and 12 are read out in series according to the supplied addresses.
The data which is read out from the period memory 12 is supplied to the test synchronizing signal generator 13. The test synchronizing signal generator 13 accesses the test synchronizing signal timing data table 13a in accordance with the supplied data (or the address value) to determine the period of the test synchronizing signal SY to be generated. The test synchronizing signal SY with the determined period is generated in the test synchronizing signal generator 13 and is supplied to the pattern memories 5, the timing memories 6, the timing generators 7 and the pattern controller 10.
The data which is read out from the timing memory 6 is supplied to the timing generator 7. The timing generator 7 accesses the timing edge data table 7a in accordance with the supplied data (or the address value) to determine the timing of the test signal TS to be generated (and the timing of executing the judgment not shown in FIG. 4). The timing signal (or set edge and reset edge signals in FIG. 4) TM with the determined timing is generated in the timing generator 7 and is supplied to the output waveform generation circuit 8 and the comparator 9.
The pattern data PT which is read out from the pattern memory 5 is supplied to the output waveform generation circuit 8 and the comparator 9. The output waveform generation circuit 8 generates an output waveform in accordance with the supplied pattern data PT and timing signal TM and outputs it as a test signal TS to the corresponding external signal terminal 3a, 3b, . . . 3n. On the other hand, though not shown in FIG. 4, the comparator 9 samples the response output from the semiconductor device 200 to be tested in the timing of the timing signal TM outputted from the timing generator 7 to make a judgment by comparing the sampled data with the pattern data PT outputted from the pattern memory 5.
In addition, algorithms of generating addresses in the pattern controller 10 are programmed by instructions in the instruction memory 11. Since the addresses of the pattern memories 5 and the timing memories 6 are communicable between all of the pin test portions 4a, 4b, . . . 4n, the algorithms of generating the test signal and executing the judgment in each of the pin test portion 4a, 4b, . . . 4n can be controlled by only one pattern controller 10 and one instruction memory 11.
According to the conventional device for testing the semiconductor device as constructed above, the addresses to the pattern memories 5 and the timing memories 6 in each of the pin test portions 4a, 4b, . . . 4n are constantly common. Therefore, also a pin test portion in which the frequencies of waveform change of the test signal TS and judgment execution are low is required to ensure the same number of addresses of the pattern memory 5 and the timing memory 6 if the waveform change of the test signal or the judgment execution occurs in other pin test portions. In FIG. 4, for example, the contents of the pattern memory 5 and timing memory 6 in the pin test portion 4b do not change for first five addresses. However, the contents of the pattern memory 5 and timing memory 6 in the pin test portion 4a change for each address. Accordingly, it is necessary for the pattern memory 5 and timing memory 6 in the pin test portion 4b to ensure the capacity for five addresses.
As a result, the capacity of all pattern memories 5 and timing memories 6 grows enormous. Furthermore, the increase in memory capacity is accompanied by an increase in the power dissipated by the test device and the enlargement of the external dimension thereof, and test programs grow so large that they are difficult to manage.